Skip to main content

Thank you for visiting nature.com. You are using a browser version with limited support for CSS. To obtain the best experience, we recommend you use a more up to date browser (or turn off compatibility mode in Internet Explorer). In the meantime, to ensure continued support, we are displaying the site without styles and JavaScript.

Logic-in-memory based on an atomically thin semiconductor

Abstract

The growing importance of applications based on machine learning is driving the need to develop dedicated, energy-efficient electronic hardware. Compared with von Neumann architectures, which have separate processing and storage units, brain-inspired in-memory computing uses the same basic device structure for logic operations and data storage1,2,3, thus promising to reduce the energy cost of data-centred computing substantially4. Although there is ample research focused on exploring new device architectures, the engineering of material platforms suitable for such device designs remains a challenge. Two-dimensional materials5,6 such as semiconducting molybdenum disulphide, MoS2, could be promising candidates for such platforms thanks to their exceptional electrical and mechanical properties7,8,9. Here we report our exploration of large-area MoS2 as an active channel material for developing logic-in-memory devices and circuits based on floating-gate field-effect transistors (FGFETs). The conductance of our FGFETs can be precisely and continuously tuned, allowing us to use them as building blocks for reconfigurable logic circuits in which logic operations can be directly performed using the memory elements. After demonstrating a programmable NOR gate, we show that this design can be simply extended to implement more complex programmable logic and a functionally complete set of operations. Our findings highlight the potential of atomically thin semiconductors for the development of next-generation low-power electronics.

Access options

Rent or Buy article

Get time limited or full article access on ReadCube.

from$8.99

All prices are NET prices.

Fig. 1: Structure of in-memory device.
Fig. 2: Characterization of non-volatile memories.
Fig. 3: Programmable inverter based on a MoS2 memory cell.
Fig. 4: Logic-in-memory.

Data availability

The data that support the findings of this study are available at http://doi.org/10.5281/zenodo.4073060.

References

  1. 1.

    Kautz, W. H. Cellular logic-in-memory arrays. IEEE Trans. Comput. C-18, 719–727 (1969).

    Article  Google Scholar 

  2. 2.

    Stone, H. S. A logic-in-memory computer. IEEE Trans. Comput. C-19, 73–78 (1970).

    Article  Google Scholar 

  3. 3.

    Le Gallo, M. et al. Mixed-precision in-memory computing. Nat. Electron. 1, 246–253 (2018).

    Article  Google Scholar 

  4. 4.

    Horowitz, M. Computing’s energy problem (and what we can do about it). In 2014 IEEE Intl Solid-State Circuits Conf. Digest of Technical Papers (ISSCC) 10–14 (IEEE, 2014).

  5. 5.

    Wang, Q. H., Kalantar-Zadeh, K., Kis, A., Coleman, J. N. & Strano, M. S. Electronics and optoelectronics of two-dimensional transition metal dichalcogenides. Nat. Nanotechnol. 7, 699–712 (2012).

    ADS  CAS  Article  PubMed  Google Scholar 

  6. 6.

    Manzeli, S., Ovchinnikov, D., Pasquier, D., Yazyev, O. V. & Kis, A. 2D transition metal dichalcogenides. Nat. Rev. Mater. 2, 17033 (2017).

    ADS  CAS  Article  Google Scholar 

  7. 7.

    Radisavljevic, B., Radenovic, A., Brivio, J., Giacometti, V. & Kis, A. Single-layer MoS2 transistors. Nat. Nanotechnol. 6, 147–150 (2011).

    ADS  CAS  Article  PubMed  PubMed Central  Google Scholar 

  8. 8.

    Bertolazzi, S., Brivio, J. & Kis, A. Stretching and breaking of ultrathin MoS2. ACS Nano 5, 9703–9709 (2011).

    CAS  Article  PubMed  Google Scholar 

  9. 9.

    Iannaccone, G., Bonaccorso, F., Colombo, L. & Fiori, G. Quantum engineering of transistors based on 2D materials heterostructures. Nat. Nanotechnol. 13, 183–191 (2018); correction 15, 520 (2018).

    ADS  CAS  Article  PubMed  PubMed Central  Google Scholar 

  10. 10.

    Wu, B., Wan, A., Iandola, F., Jin, P. H. & Keutzer, K. SqueezeDet: unified, small, low power fully convolutional neural networks for real-time object detection for autonomous driving. In 2017 IEEE Conf. Computer Vision and Pattern Recognition Workshops (CVPRW) 446–454 (IEEE, 2017).

  11. 11.

    Graves, A., Mohamed, A. & Hinton, G. Speech recognition with deep recurrent neural networks. In 2013 IEEE Intl Conf. Acoustics, Speech and Signal Processing 6645–6649 (IEEE, 2013).

  12. 12.

    Kononenko, I. Machine learning for medical diagnosis: history, state of the art and perspective. Artif. Intell. Med. 23, 89–109 (2001).

    CAS  Article  PubMed  PubMed Central  Google Scholar 

  13. 13.

    Naffziger, S. High-performance processors in a power-limited world. In 2006 Symp. VLSI Circuits, 2006. Digest of Technical Papers 93–97 (IEEE, 2006).

  14. 14.

    McKee, S. A. Reflections on the memory wall. In Proc. First Conf. Computing Frontiers CF’04 162 (ACM Press, 2004).

  15. 15.

    Xu, X. et al. Scaling for edge inference of deep neural networks. Nat. Electron. 1, 216–222 (2018).

    Article  Google Scholar 

  16. 16.

    Arute, F. et al. Quantum supremacy using a programmable superconducting processor. Nature 574, 505–510 (2019).

    ADS  CAS  Article  PubMed  Google Scholar 

  17. 17.

    Kwon, J. et al. Three-dimensional monolithic integration in flexible printed organic transistors. Nat. Commun. 10, 54 (2019).

    ADS  CAS  Article  PubMed  PubMed Central  Google Scholar 

  18. 18.

    Shulaker, M. M. et al. Three-dimensional integration of nanotechnologies for computing and data storage on a single chip. Nature 547, 74–78 (2017).

    ADS  CAS  Article  PubMed  Google Scholar 

  19. 19.

    Yu, S. Neuro-inspired computing with emerging nonvolatile memories. Proc. IEEE 106, 260–285 (2018).

    CAS  Article  Google Scholar 

  20. 20.

    Chen, W.-H. et al. CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors. Nat. Electron. 2, 420–428 (2019).

    CAS  Article  Google Scholar 

  21. 21.

    Li, C. et al. Analogue signal and image processing with large memristor crossbars. Nat. Electron. 1, 52–59 (2018).

    Article  Google Scholar 

  22. 22.

    Fuller, E. J. et al. Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing. Science 364, 570–574 (2019).

    ADS  CAS  Article  PubMed  Google Scholar 

  23. 23.

    Fiori, G. et al. Electronics based on two-dimensional materials. Nat. Nanotechnol. 9, 768–779 (2014); erratum 9, 1063 (2014).

    ADS  CAS  Article  PubMed  Google Scholar 

  24. 24.

    Splendiani, A. et al. Emerging photoluminescence in monolayer MoS2. Nano Lett. 10, 1271–1275 (2010).

    ADS  CAS  Article  PubMed  Google Scholar 

  25. 25.

    Desai, S. B. et al. MoS2 transistors with 1-nanometer gate lengths. Science 354, 99–102 (2016).

    ADS  CAS  Article  PubMed  Google Scholar 

  26. 26.

    Radisavljevic, B., Whitwick, M. B. & Kis, A. Integrated circuits and logic operations based on single-layer MoS2. ACS Nano 5, 9934–9938 (2011).

    CAS  Article  PubMed  Google Scholar 

  27. 27.

    Wachter, S., Polyushkin, D. K., Bethge, O. & Mueller, T. A microprocessor based on a two-dimensional semiconductor. Nat. Commun. 8, 14948 (2017).

    ADS  CAS  Article  PubMed  PubMed Central  Google Scholar 

  28. 28.

    Bertolazzi, S., Krasnozhon, D. & Kis, A. Nonvolatile memory cells based on MoS2/graphene heterostructures. ACS Nano 7, 3246–3252 (2013).

    CAS  Article  PubMed  PubMed Central  Google Scholar 

  29. 29.

    Li, D. et al. Nonvolatile floating-gate memories based on stacked black phosphorus-boron nitride-MoS2 heterostructures. Adv. Funct. Mater. 25, 7360–7365 (2015).

    CAS  Article  Google Scholar 

  30. 30.

    Tan, C., Liu, Z., Huang, W. & Zhang, H. Non-volatile resistive memory devices based on solution-processed ultrathin two-dimensional nanomaterials. Chem. Soc. Rev. 44, 2615–2628 (2015).

    CAS  Article  PubMed  PubMed Central  Google Scholar 

  31. 31.

    Wang, J. et al. Floating gate memory-based monolayer MoS2 transistor with metal nanocrystals embedded in the gate dielectrics. Small 11, 208–213 (2015).

    CAS  Article  PubMed  PubMed Central  Google Scholar 

  32. 32.

    Cao, W., Kang, J., Bertolazzi, S., Kis, A. & Banerjee, K. Can 2D-nanocrystals extend the lifetime of floating-gate transistor based nonvolatile memory? IEEE Trans. Electron Dev. 61, 3456–3464 (2014).

    ADS  CAS  Article  Google Scholar 

  33. 33.

    Sebastian, A., Pannone, A., Subbulakshmi Radhakrishnan, S. & Das, S. Gaussian synapses for probabilistic neural networks. Nat. Commun. 10, 4199 (2019).

    ADS  Article  PubMed  PubMed Central  Google Scholar 

  34. 34.

    Sivan, M. et al. All WSe2 1T1R resistive RAM cell for future monolithic 3D embedded memory integration. Nat. Commun. 10, 5201 (2019).

    ADS  Article  PubMed  PubMed Central  Google Scholar 

  35. 35.

    Sun, L. et al. Self-selective van der Waals heterostructures for large scale memory array. Nat. Commun. 10, 3161 (2019).

    ADS  Article  PubMed  PubMed Central  Google Scholar 

  36. 36.

    Kim, H., Ovchinnikov, D., Deiana, D., Unuchek, D. & Kis, A. Suppressing nucleation in metal–organic chemical vapor deposition of MoS2 monolayers by alkali metal halides. Nano Lett. 17, 5056–5063 (2017).

    ADS  CAS  Article  PubMed  PubMed Central  Google Scholar 

  37. 37.

    Cun, H. et al. Wafer-scale MOCVD growth of monolayer MoS2 on sapphire and SiO2. Nano Res. 12, 2646–2652 (2019).

    CAS  Article  Google Scholar 

  38. 38.

    Raja, A. et al. Dielectric disorder in two-dimensional materials. Nat. Nanotechnol. 14, 832–837 (2019).

    ADS  CAS  Article  PubMed  Google Scholar 

  39. 39.

    Papandroulidakis, G., Vourkas, I., Vasileiadis, N. & Sirakoulis, G. Ch. Boolean logic operations and computing circuits based on memristors. IEEE Trans. Circuits Syst. II 61, 972–976 (2014).

    Article  Google Scholar 

  40. 40.

    Resta, G. V. et al. Polarity control in WSe2 double-gate transistors. Sci. Rep. 6, 29448 (2016).

    ADS  CAS  Article  PubMed  PubMed Central  Google Scholar 

  41. 41.

    Resta, G. V. et al. Doping-free complementary logic gates enabled by two-dimensional polarity-controllable transistors. ACS Nano 12, 7039–7047 (2018).

    CAS  Article  PubMed  Google Scholar 

  42. 42.

    Dumcenco, D. et al. Large-area epitaxial monolayer MoS2. ACS Nano 9, 4611–4620 (2015).

    CAS  Article  PubMed  PubMed Central  Google Scholar 

Download references

Acknowledgements

We thank Z. Benes (CMI) for help with electron-beam lithography, L. Navrátilová (CIME) for the preparation of the device cross-section and R. Zamani (CIME) for help with TEM imaging. We acknowledge support from the European Union’s Horizon 2020 research and innovation programme under grant agreements 829035 (QUEFORMAL), 785219 and 881603 (Graphene Flagship Core 2 and Core 3), from the Marie Curie-Sklodowska COFUND (665667), from the H2020 European Research Council (ERC, grant 682332) as well as from the CCMX Materials Challenge grant ‘Large area growth of 2D materials for device integration’. Device preparation was carried out in part in the EPFL Centre of MicroNanotechnology (CMI). TEM imaging was carried out in the EPFL Interdisciplinary Centre for Electron Microscopy (CIME).

Author information

Affiliations

Authors

Contributions

A.K. initiated and supervised the work. G.M.M. performed the device fabrication with initial assistance of Y.Z. G.M.M. constructed the characterization setup and performed electrical measurements. Y.Z. prepared the MOCVD grown MoS2 monolayers. Z.W. performed Raman spectroscopy and growth of wafer-scale films, supervised by A.R. M.T. performed HRTEM measurements and simulations. G.M.M., A.A. and A.K. analysed the data and wrote the manuscript with input from all authors.

Corresponding author

Correspondence to Andras Kis.

Ethics declarations

Competing interests

The authors declare no competing interests.

Additional information

Peer review information Nature thanks Devin Verreck, Takhee Lee and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

Publisher’s note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Extended data figures and tables

Extended Data Fig. 1 Two-state retention time.

The drain–source conductance GDS is shown versus time. Blue curve, VPROG = –12.5 V; red curve, VPROG = +12.5 V. To predict the trend of the decay, we fit both curves using the following expression, f(x) = Axk (dashed black lines). We expect that the device has a 10-year retention.

Extended Data Fig. 2 Additional characteristics of MoS2 FGFETs.

a, Device variability. IDS versus VG curves for six different devices on the same die. b, Fresh IDS versus VG curves, corresponding to the first VG sweep carried out on these devices. Maximal gate voltage ±VG,MAX (corresponding to VPROG) is insufficient for inducing charge transfer into the floating gate memory. This shows the behaviour of the FGFET in the initial state. c, IDS versus VG for different values of VDS (red curve, 50 mV; blue curve, 100 mV; green curve, 250 mV; orange curve, 500 mV). The progressive increase of the current without a decrease in the memory window demonstrates that the memory effect is not due to capacitive charges in the contacts. d, IDS versus VG for different sweep rates. The decrease of the memory window is a function of the sweep rate. The decrease is most probably a result of charge dynamics limiting the charging and discharging of the floating gate.

Extended Data Fig. 3 Simplified band diagrams of MoS2 FGFETs.

a, Energy band diagrams of different materials comprising the FGFET before being brought into contact. EC and EV are the positions of the bottom of the conduction band and the top of the valence band, respectively. b, Programming of the floating-gate memory by electron injection into the floating gate with the application of a positive gate voltage (upper panel). Lower panel, accompanying positive shift in the threshold voltage. c, Erase operation with electron extraction from the floating gate under the application of a negative gate voltage (upper panel). Lower panel, accompanying negative shift in the threshold voltage.

Extended Data Fig. 4 Floating-gate endurance test.

IDS is shown as a function of the number of program/erase (P/E) cycles. a, Each P/E cycle consists of a 100-ms +7.5 V pulse for the erase operation, and a 100-ms −7.5 V pulse for the program operation. b, As a but with a +10.0 V pulse for erasing and a −10.0 V pulse for programming. Both measurements are taken using a constant VDS = 50 mV and on the same device.

Extended Data Fig. 5 Example of the graphical estimation of the noise margin for the inverter programmed with VPROG = 8.5 V.

Output voltage VOUT as a function of input voltage VIN (blue dots), and its mirror reflection (red dots). VOH and VOL are defined as the points where the slope of the transfer curve (VOUT as a function of VIN, blue dots) is equal to −1, whereas VIL and VIH are the corresponding values of VIN.

Extended Data Fig. 6 Circuit schematic and logic for a two-input NOR.

a, Circuit schematic for a two-input NOR. b, Logic over time for different programming states Q1, Q2. Red: time traces of input voltages VIN1 and VIN2. Orange: output curves for Q1,2 = 33, constant LOW and Q1,2 = 11, constant HIGH. Blue: output curves for Q1,2 = 21, inverter A (IN1); Q1,2 = 12, inverter B (IN2). Green: output curve for Q1,2 = 22, NOR A,B. (Here and in Extended Data Figs. 7, 8, we denote (for example) programming state ‘Q1 = 3, Q2 = 3’ by ‘Q1,2 = 33’.).

Extended Data Fig. 7 Three-input NOR.

a, Circuit schematic for a three-input NOR. b, Logic over time for different programming states Q1, Q2, Q3. Q1–3 = 111, constant HIGH; Q1–3 = 211, inverter A (IN1); Q1–3 = 112, inverter C (IN2); Q1–3 = 122, NOR B,C; Q1–3 = 212, NOR A,C; Q1–3 = 221, NOR A,B; Q1–3 = 222, NOR A,B,C.

Extended Data Fig. 8 Two-input logic-in-memory concept and interpretation.

a, Two-input schematic of the logic-in-memory concept. b, Interface model for input polarity control. c, NAND gate, Q1–4 = 2211; d, NOR gate, Q1–4 = 2332; e, XOR gate, Q1–4 = 2222. We derive the XOR canonical form by applying De Morgan’s laws.

Extended Data Fig. 9 Hardware and software implementation of the logic-in-memory programmer.

a, b, Hardware implementation of the four-memory programmer (a) and of the nine-memory programmer (b). c, Software working diagram of the programming (top) and test (bottom) blocks. d, Example of programming (left) and test (right) blocks working, using a nine-memory programmed into the following state Q1–9 = 222111111 to perform a three-input NAND operation.

Extended Data Fig. 10 Raman characterization of monolayer MoS2.

Raman spectrum of transferred MoS2 from a single crystal (which also provided the material used in this paper) using 532-nm laser excitation and a 3,000 lines mm−1 grating. The observed wavenumber difference between the A1g and E2g Raman modes of MoS2 is consistent with a monolayer. Black line is a fit to the data points (red circles).

Extended Data Fig. 11 ADF-STEM images of monolayer MoS2.

a, Atomically resolved STEM image showing a large region of monolayer MoS2. Inset, fast Fourier transform (FFT) amplitude spectrum further shows the crystalline monolayer MoS2 structure. b, A magnified filtered STEM image taken from a shows the 2H crystal structure of monolayer MoS2. c, STEM simulation image of monolayer MoS2. The intensity line profiles at bottom right of b and c are taken along the dashed lines in those images, and show the peak positions of Mo atoms and S atoms.

Extended Data Fig. 12 FGFET TEM cross-section.

a, Wide-field view of the device fabricated using the logic-in-memory process. b, Magnified view of the contact area boxed in a. c, Cross-section image of the gate stack consisting of (from bottom to top) Pt bottom gate, HfO2 blocking oxide, Pt floating gate, HfO2 tunnel oxide. The MoS2 2D channel is on top of the gate stack.

Supplementary information

Supplementary Information

Six supplementary notes and six supplementary tables, describing the operation of the floating gate memories, memory endurance test, memory configurations for realising different logic circuits, comparison with other logic-in-memory technologies, basic material characterisation and the approach used for programming the memory circuits.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Migliato Marega, G., Zhao, Y., Avsar, A. et al. Logic-in-memory based on an atomically thin semiconductor. Nature 587, 72–77 (2020). https://doi.org/10.1038/s41586-020-2861-0

Download citation

Further reading

Comments

By submitting a comment you agree to abide by our Terms and Community Guidelines. If you find something abusive or that does not comply with our terms or guidelines please flag it as inappropriate.

Search

Quick links